The present invention relates to a method and/or architecture for a programmable logic device (PLD) generally and, more particularly, to a phase lock loop (PLL) with dynamic frequency control on a PLD.
Clock signals of a programmable logic device (PLD) can be frequency multiplied, frequency divided and phase shifted using a Phase Lock Loop (PLL) or Delay Lock Loop (DLL). The PLD, the PLL and/or the DLL can be configured using configuration bits stored in memory. Complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA) use power in proportion to operating frequency. The operating frequency of the CPLD or FPGA can be changed by reconfiguring the PLL or DLL. Currently, the PLL or DLL is configured only when the CPLD or FPGA is programmed or configured (i.e., the configuration bits for PLD and PLL or DLL are written into the memory). Changing the configuration of the PLL or DLL requires that a new programming file be generated. Because the PLL or DLL is configured only when the CPLD or FPGA is programmed, the PLL or DLL is not reconfigurable xe2x80x9con the flyxe2x80x9d.
The present invention concerns an apparatus comprising a clock generating circuit and a programmable logic circuit. The clock generating circuit may be configured to generate one or more output signals in response to a reference signal and one or more control signals, wherein the output signals each have a frequency and a phase that are dynamically variable. The programmable logic circuit may be configured to generate one or more of the control signals and receive the one or more output signals.
The objects, features and advantages of the present invention include providing a PLL with dynamic frequency control on a programmable logic device (PLD) that may (i) provide a dynamically controlled skew (phase), (ii) provide improved jitter immunity, (iii) provide dynamic frequency synthesis (through control of multiply and divide values), and/or (iv) provide a PLD for the low-power or handheld markets.